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nx25f011a nx25f041a nexflash technologies, inc. 1 preliminary nxsf014b-0699 06/11/99 1 2 3 4 5 6 7 8 9 10 11 12 features ? flash storage for resource-limited systems ? ideal for portable/mobile and microcontroller-based applications that store voice, text, and data nexflash serial flash memory ? patented single transistor eeprom technology ? high-density, low-voltage & power, cost-effective ? small 264-byte sectors ? 10k/100k write cycles, ten years data retention ultra-low power for battery-operation ? single 5v or 3v supply for read and erase/write ? 1 a standby current, 5 ma active @ 3v (typical) ? low frequency read command for very low power ? no pre-erase. erase/write time of 5 ms/sector @ 5v ensures efficient battery use nx25f011a nx25f041a 1m-bit and 4m-bit serial flash memories with 4-pin spi interface preliminary june 1999 4-pin spi serial interface ? easily interfaces with popular microcontrollers ? clock operation as fast as 16 mhz on-chip serial sram ? dual 264-byte read/write sram buffers ? use in conjunction with or independent of flash ? off-loads ram-limited microcontrollers special features for media-storage applications ? byte-level addressing ? transfer and compare sector to sram commands ? versatile hardware and software write-protection ? alternate oscillator frequency for emi sensitive applications. ? in-system electronic part number identification ? removable serial flash module package option description the nx25f011a and nx25f041a serial flash memories provide a storage solution for systems limited in power, pins, space, hardware, and firmware resources. they are ideal for applications that store voice, text, and data in a portable or mobile environment. using nexflash's patented single transistor eeprom cell, the devices offer a high-density, low-voltage, low-power, and cost-effective non-volatile memory solution. the devices operate on a single 5v or 3v (2.7v-3.6v) supply for read and erase/write with typical current consumption as low as 5 ma active and less than 1 a standby. sector erase/write speeds as fast as 5 ms increase system performance, minimize power-on time, and maximize battery life. the nx25f011a and nx25f041a provide 1m -bit and 4m-bit of flash memory organized as 512 and 2048 sectors of 264 bytes each. each sector is individually addressable through basic serial-clocked commands. the 4-pin spi serial interface works directly with popular microcontrollers. special features include: on-chip serial sram, byte-level addressing, double-buffered sector writes, transfer/compare sector to sram, hardware and software write protection, alternate oscillator frequency, electronic part number, and removable serial flash module package option. develop- ment is supported with the pc- based serial flash development kit. this document contains preliminary information. nexflash reserves the right to make changes to its product at any time without notice in order to improve design and supply the best possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 1998, nexflash technologies, inc.
2 nexflash technologies, inc. preliminary nxsf014b-0699 06/11/99 nx25f011a nx25f041a functional overview an architectural block diagram of the nx25f011a and nx25f041a is shown in figure 2. key elements of the architecture include: spi interface and command set logic serial flash memory array serial sram and program buffer write protection logic configuration and status registers device information sector figure 2. nx25f011a and nx25f041a architectural block diagram device information sector (read only) write protect logic nexflash 1 and 4 megabit serial flash memory array 512 and 2048 byte-addressable sectors of 264 bytes each row decode (512 and 2048 sectors) program buffer (264 bytes) 2112 2112 8 8 8 sram (264 bytes) column decode, sense amp latch and data compare logic high-voltage generators sector-address latch data 9/10/11 write control logic hold or read/busy logic configuration register status register spi command and control logic byte-address latch/counter 9 16
nx25f011a nx25f041a nexflash technologies, inc. 3 preliminary nxsf014b-0699 06/11/99 1 2 3 4 5 6 7 8 9 10 11 12 table 1. pin descriptions si serial data input so serial data output sck serial clock input cs chip select input wp write protect input hold , r/ b hold input or read busy output vcc power supply gnd ground pin descriptions package the nx25f011a and nx25f041a are available in a 28-pin tsop (type i) surface mount package. see figure 3 and table 1 for pin assignments. all interface and supply pins are on one side of the package. the ? no connect ? (nc) pins are not connected to the device, allowing the pads and the area around them to be used for routing pcb system traces. the devices are also available in a cost-effective and space-efficient removable serial flash module package (see nx25mxxx data sheet). serial data input (si) the spi bus serial data input (si) provides a means for data to be written to (shifted into) the device. serial data output (so) the spi bus serial data output (so) provides a means for data to be read from (shifted out of) the device during a read operation. when the device is deselected ( cs =1 or hold =0) the so pin is in a high-impedance state. serial clock (sck) all commands and data written to the serial input (si) are clocked relative to the rising edge of the serial clock (sck). by default all data read from the serial data output (so) is clocked relative to the falling edge of sck, allowing compatibility with standard spi systems. the user may specify reading relative to the rising edge of sck by chang- ing the setting of the rce bit in the configuration register (see figure 6). clock rates of up to 16 mhz for 5v devices and up to 8 mhz for 3v devices are supported. chip select ( cs cs cs cs cs ) the nx25f011a and nx25f041a are selected for opera- tion when the chip select input ( cs ) is asserted low. upon power-up, an initial low-to-high transition of cs is required before any command sequence will be acknowledged. the device can be deselected to a non-active state when cs is brought high. once deselected, the so pin will enter a high-impedance state and power consumption will decrease to standby levels unless programming is in process, in which case standby will resume when program- ming is complete. write protect ( wp wp wp wp wp ) the write protect input ( wp ) works in conjunction with the write protect range set in the configuration register bits. when wp is asserted (active low) the entire flash memory array is write protected. when high, any flash memory sector can be written to unless its address is within the write protect range that is set in the configuration register. hold or ready/busy ( hold hold hold hold hold or r/ b b b b b ) this multi-function pin can serve either as a hold input ( hold ) or as a ready-busy output (r/ b ). factory-programmed as a no connect, the pin can be reconfigured as a ready-busy output or as a hold input by setting the configuration register. warning: this pin is tied low in the serial flash module and must be left as a no connect (nc). power supply pins (vcc and gnd) the nx25f011a and nx25f041a support single power supply read and erase/write operations in 5v and 3v versions. typical active power is as low as 5 ma for the 3v version with standby current less than 1 a. figure 3. nx25f011a and nx25f041a pin assignments, 28-pin tsop (type i) hold-r/b nc wp nc nc vcc gnd nc nc nc cs sck si so nc nc nc nc nc nc nc nc nc nc nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
4 nexflash technologies, inc. preliminary nxsf014b-0699 06/11/99 nx25f011a nx25f041a serial flash memory array the flash memory array of the nx25f011a and nx25f041a are organized as 512 and 2048 sectors of 264-bytes (2,112 bits) each, as shown in figure 4. group- ing sectors as pairs offers a convenient format for applica- tions that store and transfer data in a dos compatible sector size of 512-bytes. the additional 16-bytes per sector pair can be used for sector management such as header, checksum, crc, or other related application requirements. the serial flash memory of the nx25f011a and nx25f041a is byte-addressable. that is, each sector is individually addressable and each byte within a sector is individually addressable. this allows a single byte, or specified sequence of bytes, to be read without having to clock an entire 264-byte sector out of the device. data can be read directly from a sector in the flash memory array by using a read from sector command from the spi bus. data can be written to a sector in the flash memory array using a write to sector command or a transfer sram to sector command. after a sector has been written, the memory array will become busy while it is programming the specified non-volatile memory cells of that sector. this busy time will not exceed t wp (~5 ms for 5v devices), during which time the flash array is unavailable for read or write access. the device can be tested to determine the array ? s availability by reading the ready/busy status, by reading the status register, or by testing the ready/busy pin. note that the sram is always available, even when the memory array is busy. see the serial sram section for more details. the nx25f011a and nx25f041a do not require pre-erase. the device incorporates an auto-erase-before-write feature that automatically erases the addressed sector at the beginning of the write operation. this allows for fast and consistent programming times and simplifies firm- ware support by eliminating the need for a separate pre- erase algorithm and the complex management of dispro- portional erase and write block sizes commonly found in other devices. byte 0 000h sector 0 000h 25f011 s[8:0] 25f041 s[10:0] sector address: byte address: b[8:0] sector 1 001h sector 2047 7ffh sector 511 1ffh sector 2046 7feh sector 510 1feh sector 2-2045 002h-7fdh sector 2-509 002h-1fdh byte1 001h byte1 001h byte 2-261 002h-105h byte 2-261 002h-105h 1m-bit or 4m-bit serial flash memory array 512 and 2048 byte-addressable sectors of 264-bytes each byte 262 106h byte 262 106h byte 263 107h byte 0 000h byte 263 107h byte 0 000h byte 0 000h byte 1 001h byte 1 001h byte 2-261 002h-105h byte 2-261 002h-105h byte 262 106h byte 262 106h byte 263 107h byte 263 107h sector 1 001h sector 0 000h figure 4. nx25f011a and nx25f041a serial flash memory array
nx25f011a nx25f041a nexflash technologies, inc. 5 preliminary nxsf014b-0699 06/11/99 1 2 3 4 5 6 7 8 9 10 11 12 serial sram and program buffer one of the most powerful features of the nx25f011a and nx25f041a is the integrated serial sram and its associ- ated program buffer. together, the 264-byte serial sram and 264-byte program buffer provide up to 528-bytes of usable sram storage. the sram can be used in conjunction with the flash memory or independently. the main purpose of the serial sram is to serve as the primary buffer for data to be written into the serial flash memory array. using the write to sector command, data is first shifted into the sram from the spi bus. when the command sequence has been completed, the entire 264-bytes is transferred to the program buffer. the program buffer supports the array during the erase/write cycle ( t wp ), freeing the sram to accept new data. this double-buffering scheme increases erase/write transfer rates and can eliminate the need for external ram buffers (figure 5). the sram is fully byte-addressable. thus, the entire 264-bytes, a single byte, or a sequence of bytes can be read from or written to the sram. this allows the sram to be used as a temporary work area for read-modify-write operations prior to a sector write. the transfer sector to sram command allows the con- tents of a specified sector of flash memory to be moved to the sram. this can be useful when only a portion of a sector needs to be altered. in this case the sector is first transferred to the sram, where modifications are made using the write to sram command. once complete, a transfer sram to sector command is used to update the sector. spi command and control logic sck cs si so status register configuration register program buffer compare sector to sram read from device information sector read from program buffer note: 1. a single byte, several bytes, or all bytes of a flash sector, the sram, or program buffer may be addressed. 2. all double lines represent implied connections or actions. serial flash memory array 512 and 2048 byte-addressable sectors of 264-bytes each device information sector transfer sram to sector (via program buffer) write to sector (via sram & program buffer) transfer sram to program buffer transfer program buffer to sram serial sram read from or write to sram transfer sector to sram read from sector figure 5. command relationships of the spi interface, serial flash memory array, sram and program buffer
6 nexflash technologies, inc. preliminary nxsf014b-0699 06/11/99 nx25f011a nx25f041a cf15:9 (reserved) cf8 cf7 cf6 cf5 cf4 cf3 cf2 cf1 cf0 af wr3 wr2 wr1 wr0 wd rce hr1 hr0 alternate oscilator frequency write protect range write protect direction read data clock edge hold-ready/busy pin function figure 6. configuration register bit locations the compare sector command allows the contents of the sram to be compared with the specified sector in memory. the result of the compare is set in the status register. this command can be useful for verifying a sector after write (see high data integrity applications towards the end of this data sheet). it is also useful when rewriting multi-sector files that have only minor changes from the previous write. if the new data in the sram is the same as the previously written data, the sector write can be skipped. used in this way, the command saves time that would have been used for re-programming. it also extends the endurance of the flash memory cells. using the sram independent of flash memory the sram can be used independently of flash memory operations for lookup tables, variable storage, or scratch pad purposes. if the flash memory needs to be written to while sram is being used for a different purpose, the contents can be temporarily stored to a sector and then transferred back again when needed. the sram can be especially useful for ram-limited microcontroller-based systems, eliminating the need for external sram and freeing pins for other purposes. it can also make it possible to use small pin-count microcontrollers, since only a few pins are needed for the interface instead of the 20-40 pins required for parallel bus-oriented flash devices. if more than 264 bytes of sram are needed, the transfer sram to program buffer , transfer program buffer to sram , and read program buffer commands can be used to expand the storage to 528 bytes. in this mode of operation, all writes must be handled through the 264-byte sram and the program buffer is essentially used as a stack. write protection the nx25f011a and nx25f041a provide advanced software and hardware write protection features. software-controlled write protection of the entire array is handled using the write enable and write disable commands. hardware write protec- tion is possible using the write protect pin ( wp ). write-protecting a portion of flash memory is accommodated by programming a write protect range in the configuration register. for applications needing a portion of the memory to be permanently write-protected, a onetime programmable write protection feature is supported. contact nexflash for further information. configuration register the configuration register stores the current configura- tion of the hold -r/ b pin, read clock edge, write protect range, and alternate oscillator frequency (figure 6). the configuration register is accessed using the write and read configuration register commands. the non-volatile configuration register will maintain its setting even when power is removed.
nx25f011a nx25f041a nexflash technologies, inc. 7 preliminary nxsf014b-0699 06/11/99 1 2 3 4 5 6 7 8 9 10 11 12 the factory default setting for bits cf8-cf0 is: 0 0000 1001 b(write protect range = none, read uses falling edge of the clock, and pin 1 = no connect). bits cf15-cf9 are reserved. when writing to the configuration register cf15-cf9 should be 0. when reading, the settings of cf15-cf9 should be ignored. standard write endurance rating of the memory array allows for 10,000 erase/write cycles. extended endurance to 100,000 cycles is possible using ecc techniques like those provided in the serial flash development kit. the rating of the configuration register eeprom cells is 1,000 write cycles. this is more than adequate considering the configuration seldom needs to be changed. to mini- mize writes to the configuration register, the configuration register should be read upon power-up to determine if a change is required. if no change is needed, the write configuration command can be skipped. this process will extend the life of the configuration register and save processing time (figure 7). alternate oscillator frequency, af flash memory devices have charge pump oscillators to generate internal high-voltages used for programming non-volatile memory cells. in some applications, the oscil- lator frequency of the charge pump may cause noise interference. to solve this problem, an alternate oscillator frequency (af) can be selected by setting bit cf[8] of the configuration register. the alternate frequency is a non-harmonic frequency of the standard oscillator. the factory default setting is for the standard oscillator frequency, af equal to 0. af=0 standard oscillator frequency is used. af=1 alternate oscillator frequency is used. write protect range and direction, wr[3:0], wd the write protect range and direction bits wr[3:0] and wd are located at configuration bits cf[7:4] and cf[3] respec- tively. the write protect range and direction bits select how the array is protected. they work in conjunction with the wp input pin, valid only if wp is inactive (high). wr[3:0] can select write protection of all sectors, none of the sectors, or specific sectors grouped in blocks of 32 (~8 kb). the wd bit specifies whether the protected block range starts from the first sector, address 0 (000h), or from the last sector (1ffh for the nx25f011a and 7ff for the nx25f041a). table 2 lists the write protect sector range for both devices. once protected, all further writes to sectors within the range will be ignored. the factory default setting is with no write protected sectors, wr=[0,0,0,0] and wd=1. read clock edge, rce the read clock edge bit (rce) is located at configuration bit location cf[2]. it selects which edge of the clock (sck) is used while reading data out of the device. although the spi protocol specifies that data is written during the rising edge and read on the falling edge of the clock, the output can be driven on the rising edge of the clock by setting the configuration registers rce bit to a 1. using the rising edge of clock for data reads may be beneficial to the timing of some high-speed systems. the factory default setting is for reading on the falling edge of sck. rce=0 read data is output on the falling edge of sck. rce=1 read data is output on the rising edge of sck. figure 7. flow chart for checking the configuration register upon power-up system power-up read device information sector, verify device density and type read configuration register verify bits are set as needed configuration setting is correct? yes write configuration register to correct setting application routines no
8 nexflash technologies, inc. preliminary nxsf014b-0699 06/11/99 nx25f011a nx25f041a hold hold hold hold hold -r/ b b b b b , hr[1:0] the hold-ready/busy ( hold -r/ b ) bits hr1 and hr0 are located at bits cf[1:0] of the configuration register. these two bits select one of four possible functions: no connect, hold input, r/ b output, or r/ b output with open drain. the factory setting for the pin is ? no connect ? . warning: this pin is tied low in the serial flash module and must be left as a no connect (nc) for serial flash module applications. hr1 hr0 pin configuration 00 hold input 0 1 no connect 10r/ b output (open drain) 11r/ b output configured as a r/ b output, the pin can serve as a system interrupt. when r/ b is high, the array is ready to be programmed. when r/ b is low, it is busy programming. if configured with an open-drain, an external pull-up resistor should be used. as a hold input, the pin can be used in conjunction with the cs and sck pin to suspend a serial command sequence without resetting the command. this can be useful if a command is in process and a higher priority task on the same spi bus needs to be attended to. to suspend a command, hold must be brought low while cs and sck are low. with hold low, further data on the si pin is ignored (even while sck is clocked) and the so pin goes to a high-impedance state. to resume the command sequence, hold must be brought high when cs and sck are low. see timing diagrams. status register bit descriptions the status register provides status of the flash array ? s ready/busy condition (r/ b ), transfers between the sram and program buffer (tx), write-enable/disable (we), and compare not equal (cne). the register can be read using the read status register command (figure 8). ready/busy status, busy the busy status bit is located at bit st[7] of the status register. testing the busy bit is one of several ways to check ready/busy status of the array. at power-up the busy bit is reset to 0. busy=1 the memory array is busy programming. busy=0 the memory array is ready for further use. sram and program buffer transfer, tr the tr status bit is located at bit st[6] of the status register. the bit provides status primarily for use during the transfer sram to program buffer command and transfer program buffer to sram command. an active state 1 indicates a transfer is in process and the sram or program buffer is not available for use. the device will indicate a busy state while the tr bit is active. upon power up the tr bit resets to 0. tr=1 sram and program buffer transferring. tr=0 sram and program buffer not transferring. write enable/disable, we the we status bit is located at bit st[4] of the status register. the bit provides write protect status of global write enable and write disable commands. upon power- up the we bit resets to 0. we=1 write enabled, array can be written to. we=0 write disabled, array can not be written to. the we status bit can also be used to determine the state of the wp (write protect) pin. this can be done by first issuing the write enable command and then reading the we status bit. if the status bit indicates a "0" (write disabled) then the wp pin is likely held low. table 2. write protect range sector selection (hex) write protect range config. bits write protected sectors wr3 wr2 wr1 wr0 wd=0 wd=1 (1) 0 0 0 0 none none 0 0 0 1 000 - 01fh x e0 - 1ff/ 7ffh 0 0 1 0 000 - 03fh x c0 - 1ff/ 7ffh 0 0 1 1 000 - 05fh x a0 - 1ff/ 7ffh 0 1 0 0 000 - 07fh x 80 - 1ff/ 7ffh 0 1 0 1 000 - 09fh x 60 - 1ff/ 7ffh 0 1 1 0 000 - 0bfh x 40 - 1ff/ 7ffh 0 1 1 1 000 - 0dfh x 20 - 1ff/ 7ffh 1 0 0 0 000 - 0ffh x 00 - 1ff/ 7ffh 1 0 0 1 000 - 11fh y e0 - 1ff/ 7ffh 1 0 1 0 000 - 13fh y c0 - 1ff/ 7ffh 1 0 1 1 000 - 15fh y a0 - 1ff/ 7ffh 1 1 0 0 000 - 17fh y 80 - 1ff/ 7ffh 1 1 0 1 000 - 19fh y 60 - 1ff/ 7ffh 1 1 1 0 000 - 1bfh y 40 - 1ff/ 7ffh 1 1 1 1 all all note: 1. nx25f011a x=1 y=0 and nx25f041a x=7 y=6,
nx25f011a nx25f041a nexflash technologies, inc. 9 preliminary nxsf014b-0699 06/11/99 1 2 3 4 5 6 7 8 9 10 11 12 busy tr st7 x st6 we st5 x st4 cne st3 x st2 x st1 st0 x = reserved read/busy sram and program buffer transfer flash array write enable/disable sector-sram compare not equal figure 8. status register bit locations compare not equal, cne the cne status bit is located at bit st[3] of the status register. the bit provides a cumulative comparison result during a compare sector with sram command. the cne bit is reset to a 0 upon power-up or after a clear compare bit command is executed. cne=1 sector and sram contents are not equal. cne=0 sector and sram are equal or cne bit reset. command set the nx25f011a and nx25f041a have a powerful com- mand set that is fully controlled through the spi bus. command relations are shown in figure 5 and a list of commands and their associated address, status, clock, and data bytes are shown in table 3. detailed clock timing of the read sector and write sector command sequences are shown in figures 10 and 11. after power up, a device enters an idle state that will maintain until cs pin is asserted low. all commands are entered from the spi serial data input (si) pin on the rising edge of sck while cs is asserted low. all command, address, and configuration bits are shifted into the device with most-significant-bit-first. data bits read from the device are shifted out with least significant byte first (i.e., byte-00h, byte-01h,...). the bit order within each byte is most-significant-bit first (i.e.,d7,...d0). all com- mands are completed by asserting the cs pin high. note that the entire 264-byte contents of a flash sector, the sram, or program buffer does not have to be ac- cessed all at once. read, write, transfer, and compare commands allow for byte addressing. thus a single byte, or clocked sequence of bytes, can be accessed at any starting location within the 264-byte boundary as specified by the byte-address field.
10 nexflash technologies, inc. preliminary nxsf014b-0699 06/11/99 nx25f011a nx25f041a 00000000 c[7:0] command s[15:0] sector address b[15:0] byte address rb[15:0] ready/busy status (9999h=ready) high-z so output is driven 1 st byte of data 2nd byte of data 16 clocks high-z last byte of data n-bytes of data idle cs sck si sck si so sck so cs sck so c7 c6 c5 c4 c3 c2 c1 c0 0 0 0 0 0 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 0 0 0 0 0 0 0 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 1 00110 011 0011 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d4 d5 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 idle figure 10. read from sector command sequence d7 d6 d5 d4 d3 d2 d1 d0 c[7:0] command s[15:0] sector address b[15:0] byte address last byte of data n-bytes of data t wp program time cs sck si sck si cs sck si c7 c6 c5 c4 c3 c2 c1 c0 0 0 0 0 0 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 0 0 0 0 0 0 0 b8 b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 idle 1 st byte of data 2nd byte of data d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 8 clocks figure 11. write to sector command sequence
nx25f011a nx25f041a nexflash technologies, inc. 11 preliminary nxsf014b-0699 06/11/99 1 2 3 4 5 6 7 8 9 10 11 12 serial flash sector commands read from sector reading from a sector is accomplished by first bringing cs low then shifting in the read from sector command (52h) followed by its 16-bit ? sector-address ? field. although the sector-address field is 16-bits, only bits s[8:0] for the nx25f011a (0-1ffh) and s[10:0] for the nx25f041a (0-7ffh) are used. the uppermost sector address bits are not used but must be clocked using 0 for data. next a 16-bit ? byte-address ? field is clocked into the device to designate the starting location within the 264-byte sector. only b[8:0] of the byte-address field are used; the uppermost bits are not used but must be clocked in (use 0 for data). only byte-addresses of 0 to 107h (264 bytes) are valid. table 3. command set for the nx25f011a, and nx25f041a serial flash memory n - bytes command name byte 0 byte 1-2 byte 3-4 ( italics indicate device output ) serial flash sector commands read from sector 52h sector addr. byte add. 0000h ready/busy read data read from sector low frequency 51h sector addr. byte add. 0000h ready/busy read data write enable* 06h 00h write disable* 04h 00h write to sectorf3h sector addr. byte add. write data 00h transfer sram to sector f3h sector addr. 0000h transfer sector to sram 54h sector addr. byte add. clock 00h per byte 00h compare sector with sram 86h sector addr. byte add. 0000h ready/busy bit compare of data serial sram program buffer commands write to sram** 82h 0000h byte add. write data 00h read from sram* 81h 0000h byte add. 0000h read/busy read data transfer sram to prog. buffer 92h 0000h 0000h 0000h transfer prog. buffer to sram 55h 0000h 0000h 0000h read from program buffer 91h 0000h byte add. 0000h ready/busy read data configuration and status commands read configuration register* 8bh 0000h 0000h 0000h ready/busy configuration write configuration register 8ah configuration 0000h read status register* 83h 0000h 0000h 0000h ready/busy status clear compare status* 89h 0000h read device information sector 15h 0000h byte add. 0000h ready/busy read data notes: 1. * command may be used when device is busy 2. ** command may not be used when device is busy and tr bit=0
12 nexflash technologies, inc. preliminary nxsf014b-0699 06/11/99 nx25f011a nx25f041a write enable command 8 clocks si 06h 00h so write enable upon power-up, the flash memory array is write- protected until the write enable command (06h) has been issued. the wp pin must be inactive while writing the command for the write enable to be accepted. the status of the device ? s write protect state can be read in the status register. the write enable command sequence is completed by assert- ing cs high after eight additional clocks. read from sector command sector address* byte address** 16 clocks si so 52h s[15:0] b[15:0] 0000h rb[15:0] first byte - last byte read/busy status read sector data *the sector address only uses bits [8:0], [9:0] or [10:0] **the byte address only uses bits [8:0] following the byte-address field, 16 control clocks are required with data=0. the serial data output (so) will change from a high-impedance state and begin to drive the output with ready/busy status rb[15:0]. if so uses the rising edge of clock (configuration register rce=1), the output will be driven after the last control clock. if so uses the falling edge of clock (rce=0), the output will be driven on the next falling edge of clock. if the array is not busy, the output status will be 9999h, followed by the sector data on the so pin. if the array is busy, the status will be 6666h, and the command should be terminated and restarted after a ready state occurs. the data field is shifted out with the least significant byte first (i.e., byte-00h, byte-01h, ...). the bit order within each byte is the most significant bit first (i.e.,d7,...d0). the byte-address is internally incremented to the next higher byte address as the clock continues. when the highest byte-address (107h) is reached, the address counter rolls over to byte-0h and continues to increment. asserting the cs pin high completes (or terminates) the command. detailed timing for the read from sector command is shown in figure 10. read sector (low frequency) the read sector at low frequency command (51h) can reduce power consumption during read operations by 25%-40% when the system clock frequency is 1 mhz or lower. the command sequence is identical to the standard read from sector command. write disable command 8 clocks si 04h 00h so write disable the write disable command (04h) protects the flash memory array from being programmed. once issued, further write to sector or transfer sram to sector com- mands will be ignored. the status of the write protect state can be read in the status register. the write disable command sequence is completed by asserting cs high after eight additional clocks.
nx25f011a nx25f041a nexflash technologies, inc. 13 preliminary nxsf014b-0699 06/11/99 1 2 3 4 5 6 7 8 9 10 11 12 the bit order within each byte is most significant bit first (i.e., d7,...d0). the byte-address is automatically incre- mented to the next higher byte address as the clock continues. when the last byte address to be written is reached, the command can be completed with an additional eight control clocks (with data=0) followed by asserting cs high. if the clock continues to increment past the highest byte-address (107h), the address counter will roll over to byte 0h. after the cs pin is brought high, the data in the sram is automatically transferred to the program buffer, which handles the self-timed programming of the specified sector in memory array. see t wp timing specifications. during this time the array will be ? busy ? and will ignore further array-related commands until complete. all ready/busy status indicators will indicate a busy status. since the program buffer handles all array program- ming, the sram is still available to be read from or written to during the busy state. this allows the sram to be written to in preparation of the next sector write. once the sram is loaded, its contents can be transferred to a selected sector using the transfer sram to sector command. n ote that if the write operation is to be verified the contents of the sram should be maintained. detailed clock timing for the write to sector command is shown in figure 11. write to sector before writing to a sector in the flash memory array, all hardware and software write protection must be in an enabled state. this means that the wp pin must be in a high state, a write enable command must have previ- ously been issued, and the sector location that is to be written to must be outside the write protect range set in the configuration register. additionally, the ready/busy status should be checked to confirm that the memory array is available to be written to. writing to a sector is accomplished by first bringing cs low and shifting in the write to sector command (f3h) followed by a 16-bit ? sector-address ? field. although the sector-address field is 16-bits, only bits s[8:0] for the nx25f011a (0-1ffh) and s[10:0] for the nx25f041a (0-7ffh) are used. the uppermost sector address bits are not used but must be clocked in (use 0 data). following the sector address, a 16-bit ? byte-address ? field is clocked into the device to designate the starting location within the 264- byte sector. only bits b[8:0] of the byte-address field are used and only values of 0-107h (264 bytes)are valid. after the byte-address has been loaded, data is shifted into the 264-byte sram, which serves as a temporary storage buffer. existing data in the sram will be written over. the byte order of the data shifted into the sram is least significant byte first (i.e., byte-00h, byte-01h,...). write to sector command 8 clocks si f3h s[15:0] b[15:0] first byte - last byte 00h so sector address* byte address** write sector data *the sector address only uses bits [8:0] or [10:0] **the byte address only uses bits [8:0] program time ( t wp ) transfer sram to sector the transfer sram to sector command (f3h) will write the existing contents of the sram to the specified sector in memory. the command sequence is identical to that of the write to sector command except that immediately after the sector address field s[15:0] and 16 control clocks, the cs pin is asserted high. this automatically transfers the 264-bytes of sram data to the program buffer, which handles the programming of the specified sector in the memory array. during this time, the array will be busy. since the entire 264-bytes are trans- ferred, the byte-address field b[15:0] is not used. transfer sram to sector command sector address* 16 clocks si so f3h s[15:0] 0000h *the sector address only uses bits [8:0] or [10:0] program time ( t wp )
14 nexflash technologies, inc. preliminary nxsf014b-0699 06/11/99 nx25f011a nx25f041a compare sector with sram command sector address* byte address** 16 clocks si so 86h s[15:0] b[15:0] 0000h rb[15:0] first byte - last byte read/busy status bit compare of sector and sram *the sector address only uses bits [8:0] or [10:0] **the byte address only uses bits [8:0] compare sector to sram the compare sector to sram command does a bit-by-bit comparison of the data stored in the addressed sector against data in the sram. the command is similar to the read from sector command except that data is not read out of the serial output pin (so). instead, the so pin provides a bit-by-bit compare of each sector and sram bit. a high (1) per bit will be output if the bit compare is equal. a low (0) per bit will be output if the bit compare is not equal. the compare can start from any location in the 264-byte range as specified by the byte-address field b[15:0]. the byte-address counter is automatically incremented and will wrap around to the first address (0h) if it passes the last address (107h). if any of the compared bits are not equal, then the compare not equal (cne) bit in the status register is set to a 1. this bit will stay set until a clear compare status command has been issued. transfer sector to sram command 8 clocks si 54h s[15:0] b[15:0] si=00h during byte transfers 00h so sector address* byte address** 8 clocks per byte trasnfered from first byte to last byte *the sector address only uses bits [8:0] or [10:0] **the byte address only uses bits [8:0] transfer sector to sram the transfer sector to sram command (54h) allows the contents of a sector to be transferred directly to the sram without having to read the sector out of the device and rewrite it into the sram. the command is similar to the write to sector command except that instead of inputting data from the si pin, the data is taken from the specified sector and is transferred to the sram. every eight clocks on sck, a byte from the specified sector to the sram will be transferred. although data on si is ignored, it is recom- mended to write data bytes of 00h in order to support the clocking requirements. during the transfer, the so output is in a high-impedance state. when the last byte address is transferred, the command can be completed by issuing eight more control clocks and asserting cs high. if the clock continues to increment past the highest byte-address (107h), the address counter will roll over to byte-0h.
nx25f011a nx25f041a nexflash technologies, inc. 15 preliminary nxsf014b-0699 06/11/99 1 2 3 4 5 6 7 8 9 10 11 12 serial sram and program buffer commands write to sram command the write to sram command (82h) provides access to the 264-byte sram independently of any flash memory array operation. the command is similar to the write to sector command sequence except that the sector address field s[15:0] is replaced by all 0 bits. when cs is asserted high to complete the command, the contents of the sram will be maintained until overwritten via another command or the power is removed. using the write to sram command, data can be loaded in prepara- tion of writing to a sector in memory and then transferred to a selected sector using the transfer sram to sector command. write to sram command 8 clocks si 82h 0000h b[15:0] first byte - last byte 00h so 16 clocks byte address* write sector data *the byte address only uses bits [8:0] read from sram command 16 clocks byte address* 16 clocks si so 81h 0000h b[15:0] 0000h rb[15:0] first byte - last byte read/busy status read sram data *the byte address only uses bits [8:0] read from sram the read from sram command (81h) provides access to the 264-byte sram independent of any flash memory array operations. the command is similar to the read from sector command except for the sector address field s[15:0] which is replaced with all 0 bits.
16 nexflash technologies, inc. preliminary nxsf014b-0699 06/11/99 nx25f011a nx25f041a read from program buffer command 16 clocks byte address* 16 clocks si so 91h 0000h b[15:0] 0000h rb[15:0] first byte - last byte read/busy status read program buffer data *the byte address only uses bits [8:0] read from program buffer command the read from program buffer command (91h) provides access to the 264-byte program buffer. the command is similar to the read from sector command except that the sector address field s[15:0] is replaced with all 0 bits. this command can be useful in applications where the sram and program buffer are used independently of the flash memory. this command cannot be used while the device is busy. transfer sram to program buffer the transfer sram to program buffer command transfers all 264 bytes from the sram to the program buffer at one time without the clock sequencing required in the transfer sector to sram command. this command can be useful in applications where the sram and program buffer are to be used independently of the flash memory. effective use of the transfer to sram or program buffer commands allow the two 264-byte buffers to act as 528-bytes of user sram. the command sequence is similar to the write or read sram commands except that the sector address field s[15:0] and byte address b[15:0] field are replaced with all 0 bits. after the last byte address is transferred, the command is completed by issuing 16 control clocks and then asserting cs high. there is a required delay time after cs is asserted high (see t xp timing specifica- tion). during this time the data from the sram is being transferred to the program buffer and neither are avail- able for use. status of this operation can be checked by testing the transfer in process bit (tr) in the status register. transfer sram to program buffer command 16 clocks 16 clocks 16 clocks si so 92h 0000h 0000h 0000h transfer time ( t xp )
nx25f011a nx25f041a nexflash technologies, inc. 17 preliminary nxsf014b-0699 06/11/99 1 2 3 4 5 6 7 8 9 10 11 12 transfer program buffer to sram command 16 clocks 16 clocks 16 clocks si so 55h 0000h 0000h 0000h transfer time ( t xp ) transfer program buffer to sram the transfer program buffer to sram command (55h) provides access to the 264-byte program buffer. the command sequence is similar to the write or read sram commands except that the sector address field s[15:0] and byte address b[15:0] field are replaced with all 0 bits. after the last byte address is transferred, the command is completed by issuing 16 control clocks and then asserting cs high. there is a delay time after cs is asserted high (see t xp timing specification). during this time the data from the program buffer is being transferred to the sram and neither are available for use. status of this operation can be checked by testing the transfer in process bit (tr) in the status register. this command cannot be used while the device is busy. read configuration register command 16 clocks 16 clocks 16 clocks si so 8bh 0000h 0000h 0000h rb[15:0] cf{15:0}* read/busy status read configuration bits *the cf register only uses bits [8:0] configuration and status commands read configuration register the read configuration register command provides access to the configuration register, which stores the current configuration of the hold -r/ b pin, read clock edge, write protect range, and alternate oscillator frequency (figure 6). the command sequence is similar to the read from sector command except that the sector address field s[15:0] and the byte-address field b[15:0] are replaced with all 0 bits. after 16 control clocks and after the ready/busy status field has been clocked through, a 16-bit configuration data field cf[15:0] provides the contents of the configuration register. although the field is 16-bits long, only bits cf[8:0] are used. all other upper bits are reserved for future features.
18 nexflash technologies, inc. preliminary nxsf014b-0699 06/11/99 nx25f011a nx25f041a read status register the read status register command provides access to the status register and its status flags for ready/busy (r/ b ), sram and program buffer transfer operations (tx), write enable/disable ( we ), and compare not equal (cne) (figure 8). the command sequence is similar to the 0 command except that the sector address field s[15:0] and the byte-address field b[15:0] are replaced by all 0 bits. after 16 clocks and the ready/busy status field rb[15:0] has been read, an 8-bit status field st[7:0] provides the contents of the status register. read status register command 16 clocks 16 clocks 16 clocks si so 83h 0000h 0000h 0000h rb[15:0] st[7:0] read/busy status read status register bits write configuration register the write configuration register command provides access to the configuration register which stores the current configuration of the hold -r/ b pin, read-data clock edge, write protect range, and alternate oscillator frequency. the configuration register is non-volatile. once set using the write configuration register command, the contents will maintain even when power is removed. because the register ? s state is stored in non-volatile memory, there is a finite endurance limit to the number of times it can be written to. to limit the number of writes, it is recommended that before writing to the configuration register it should first be read from using the read configuration register command. if no change is required, the write configuration register command can be skipped. this process will help extend the endurance of the configuration register bits and eliminate additional programming ? busy ? time. the write configuration register command sequence starts with the command byte (8ah) followed by a 16-bit *the cf register only uses bits [8:0] configuration bits* write configuration register command 16 clocks si 8ah cf[15:0] 0000h so field that specifies configuration register bit settings. although the field is 16-bits long, only bits cf[8:0] are used. all other upper bits are reserved and must be clocked using 0 for data. after an additional 16 control clocks using 0 for data, the command can be completed by asserting cs high. the device will become busy for a short time ( t wp ) while the non-volatile memory cells of the configuration register are programmed.
nx25f011a nx25f041a nexflash technologies, inc. 19 preliminary nxsf014b-0699 06/11/99 1 2 3 4 5 6 7 8 9 10 11 12 read device info. sector command 16 clocks byte address* 16 clocks si so 15h 0000h b[15:0] 0000h rb[15:0] first byte - last byte read/busy status read sector data *the byte address only uses bits [8:0] read device information sector the read device information command provides access to a read-only sector that can be used to electronically identify the nexflash serial flash device being used. information available includes: part number, density, voltage, temperature range, package type, and any special options. this can be extremely useful for sys- tems that need to accommodate optional densities (e.g., both 1m-bit and 4m-bit). in this case the firmware can interrogate the device information sector and deter- mine the density. the device information sector also includes a list of any restricted sectors that might exist in the device. r efer to application note sfan-02 for more detailed information on the device information sector format. clear compare status command 8 clocks si 89h 00h so clear compare status the clear compare status command (89h) works in conjunction with the compare sector to sram command and the status register. if any of the compared bits are not equal, then the compare not equal (cne) bit in the status register is set to a 1. the clear compare status command must be executed to reset the cne bit to a 0.
20 nexflash technologies, inc. preliminary nxsf014b-0699 06/11/99 nx25f011a nx25f041a no more retries no yes retry write verify return error write to sram command transfer sram to sector command compare sector with sram command ready? programming done? equivalent retry counter no yes figure 12. write/verify flow for high data integrity applications sector format and tag/sync bytes the first byte of each sector is pre-programmed during manufacturing with a tag/sync value of c9h. although this byte location of the sector can be changed, it is recom- mended that it be maintained and incorporated into the application ? s sector formatting. the tag/sync values serve two purposes. first, they provide a sync-detect that can help verify if the command sequence was clocked into the device properly. secondly, they serve as a tag to identify a fully functional (valid) sector. this is especially important if ? restricted sector ? devices are to be used. restricted sector devices have a limited number of sectors that do not meet manufacturing programming criteria over the specified operating range. when such a sector is detected, the first byte is tagged with a pattern other than c9h. in addition to individual sector tagging, all restricted sectors for a given device are listed in the device information sector. for more information see the device information sector application note sfan-02. high data integrity applications data storage applications that use flash memory or other non-volatile media must take into consideration the possi- bility of noise or other adverse system conditions that may affect data integrity. for those applications that require higher levels of data integrity it is a recommended practice to use error correcting code (ecc) techniques. the nexflash serial flash development kit provides a soft- ware routine for a 32-bit ecc that can detect up to two bit errors and correct one. the ecc not only minimizes problems caused by system noise but can also extend flash memory endurance. for those systems without the processing power to handle ecc algorithms, a simple ? verification after write ? is recommended (figure 12). the serial flash development kit software includes a simple write/verify routine that will compare data written to a given sector and rewrite the sector if the compare is not correct.
nx25f011a nx25f041a nexflash technologies, inc. 21 preliminary nxsf014b-0699 06/11/99 1 2 3 4 5 6 7 8 9 10 11 12 absolute maximum ratings (1) symbol parameters conditions range unit vcc supply voltage 0 to 7.0 v v in , v out voltage applied to any pin relative to ground ? 0.5 to vcc + 0.5 v t stg storage temperature ? 65 to +150 c t lead lead temperature soldering 10 seconds +300 c note: 1. this device has been designed and tested for the specified operation ranges. proper operation outside of these levels is not guaranteed. exposure beyond absolute maximum ratings (listed above) may cause permanent damage. operating ranges symbol parameter conditions min max unit vcc supply voltage 5.0v 4.5 5.5 v 3.0v 2.7 3.6 v t a ambient temperature, operating commercial 0 +70 c extended ? 20 +70 c industrial ? 40 +85 c dc electrical characteristics symbol parameter conditions min typ max unit v il input low voltage ? 0.4 ? vcc x 0.2 v v ih input high voltage vcc x 0.6 ? vcc + 0.5 v v ol output low voltage i ol = 2 ma v cc = 4.5v ?? 0.45 v v oh output high voltage i oh = ? 400 a v cc = 4.5v 2.4 ?? v v olc output low voltage cmos v cc = min, i ol = 10 a ?? 0.15 v v ohc output high voltage cmos v cc = min, i oh = ? 10 av cc ? 0.3 ?? v i il input leakage 0 < v in < vcc ? 10 ? +10 a i ol i/o leakage 0 < v in < vcc ? 10 ? +10 a i cc (active) active power supply current f clk @ 8 mhz (1/t cp )v cc = 5v ? 15 30 ma v cc = 3v ? 510ma i cclf active current low f clk @1 mhz (1/t cp )v cc = 5v ? 10 20 ma (low frequency) frequency. read v cc = 3v ? 47ma i ccsb (standby) standby power supply current cs = v cc , v in = vcc or 0 ? <1 10 a c in input capacitance (1) t a = 25 c, v cc = 5v or 3v ?? 10 pf frequency = 1 mhz c out output capacitance (1) t a = 25 c, v cc = 5v or 3v ?? 10 pf frequency = 1 mhz note: 1. tested on a sample basis or specified via design or characterization data.
22 nexflash technologies, inc. preliminary nxsf014b-0699 06/11/99 nx25f011a nx25f041a ac electrical characteristics 16 mhz 8 mhz symbol description min typ max min typ max unit t cyc sck serial clock period (1) 62 ?? 125 ?? ns t wh sck serial clock high or low time 26 ?? 57 ?? ns t wl t ri sck serial clock rise or fall time (2) ?? 7 ?? 10 ns t fi t su data input setup time to sclk 40 ?? 100 ?? ns t h data input hold time from sclk 0 ?? 0 ?? ns t v data output valid after sclk (1,3) vcc = 5.0v ?? 60 ?? 70 ns vcc = 3.0v ??? ?? 115 ns t lead cs setup time to command vcc = 5.0v 100 ?? 150 ?? ns vcc = 3.0v ??? 300 ?? ns t lag cs delay time after command vcc = 5.0v 100 ?? 150 ?? ns vcc = 3.0v ??? 300 ?? ns t wp erase/write program time vcc = 5.0v ? 510 ? 510 ms (see write to sector command) vcc = 3.0v ? 5 ?? 510 ms t xp transfer program-buffer/sram vcc = 5.0v ?? 100 ?? 100 s (see transfer pb/sram command) vcc = 3.0v ??? ?? 200 s t hd sck setup time to hold 10 ?? 20 ?? ns t cd sck hold time from hold 30 ?? 50 ?? ns t cs cs deselect time 160 ?? 200 ?? ns t rb ready / busy valid time 160 ?? 200 ?? ns t dis data output disable time ?? 160 ?? 200 ns t ho data output hold time 0 ?? 0 ?? ns notes: 1. to achieve maximum clock performance, the read clock edge will need to be set for rising edge operation in the configuration register (rce=1). 2. test points are 10% and 90% points for rise/fall times. all others timings are measured at 50% point. 3. with 50 pf (8 mhz) or 30 pf (16 mhz) load so to gnd.
nx25f011a nx25f041a nexflash technologies, inc. 23 preliminary nxsf014b-0699 06/11/99 1 2 3 4 5 6 7 8 9 10 11 12 cs sck so lsb lsb+1 msb-1 msb si t v t cyc t h t wl t wh t lag t dis serial output timing serial input timing (high impedance) t h msb msb-1 lsb lsb+1 t lead t lag t cs t rb t su t wp t xp t ri t fi cs r/ b sck si so cs hold sck so si t hd t cd t hd t cd t hz t hz hold timing
24 nexflash technologies, inc. preliminary nxsf014b-0699 06/11/99 nx25f011a nx25f041a package information plastic tsop - 28-pins package code: v (type i) plastic tsop (v ? type i) millimeters inches symbol min max min max ref. std. no. leads 28 a 1.00 1.20 0.039 0.047 a1 0.05 0.20 0.002 0.008 b 0.15 0.25 0.006 0.010 c 0.10 0.20 0.004 0.008 d 7.90 8.10 0.311 0.319 e 11.60 11.80 0.457 0.465 h 13.30 13.50 0.524 0.531 e 0.55 bsc 0.022 bsc l 0.50 0.70 0.020 0.028 0 5 0 5 notes: 1. controlling dimension: millimeters, unless other- wise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. d seating plane b e c 1 e a1 h l n a
nx25f011a nx25f041a nexflash technologies, inc. 25 preliminary nxsf014b-0699 06/11/99 1 2 3 4 5 6 7 8 9 10 11 12 ordering information size order part no. (1) package (2) 1m-bit nx25f011a-3v-r spi, 28-pin, tsop (type i) <32 rs, 3v low voltage 1m-bit nx25f011a-3v spi, 28-pin, tsop (type i) 3v low voltage (no restricted sectors) 1m-bit nx25f011a-5v-r spi, 28-pin, tsop (type i) <32 rs, 5v standard voltage 1m-bit nx25f011a-5v spi, 28-pin, tsop (type i) 5v standard voltage (no restricted sectors) 4m-bit nx25f041a-3v-r spi, 28-pin, tsop (type i) <32 rs, 3v low voltage 4m-bit nx25f041a-5v-r spi, 28-pin, tsop (type i) <32 rs, 5v standard voltage note : 1. add e (extended) or i (industrial) after package designator (v) for alternative temperature grade devices. 2. for serial flash module package see 25mxxx data sheet. 3. rs = restricted sector.
26 nexflash technologies, inc. preliminary nxsf014b-0699 06/11/99 nx25f011a nx25f041a preliminary designation the ? preliminary ? designation on an nexflash data sheet indicates that the product is not fully characterized. the specifications are subject to change and are not guaran- teed. nexflash or an authorized sales representative should be consulted for current information before using this product. important notice nexflash reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. nexflash assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user ? s specific application. while the information in this publication has been carefully checked, nexflash shall not be liable for any damages arising as a result of any error or omission. life support policy nexflash does not recommend the use of any of it's products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure in the life support system or to signifi- cantly affect its safety or effectiveness. products are not authorized for use in such applications unless nexflash receives written assurances, to it ? s satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of nexflash is adequately protected under the circumstances. trademarks: nexflash is a trademark of nexflash technologies, inc . all other marks are the property of their respective owner.

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